This invention relates generally to integrated circuit manufacturing methods and more particularly to methods used in fabricating dynamic random access memories (DRAMs).
As is known in the art, DRAMs are being used extensively in a wide range of application. A DRAM typically includes as an array of memory cells, each cell comprising a metal oxide semiconductor field effect transistor (MOSFETs) and electrically connected capacitor. When the cell is addressed, a logic state, such as a logic 1 state, is stored as a charge its capacitor.
One technique used to form the capacitor is to etch a trench in a semiconductor, typically silicon, substrate. A pad layer, typically about 500 Angstroms thick, of silicon dioxide is thermally grown over the silicon substrate. A thicker, typically 2000-10000 Angstrom mask layer of silicon nitride is then formed over the pad layer. A window is formed in a portion of the silicon nitride layer and through the underlying portion of the pad layer. The trench is then etched into the underlying, exposed portion of the silicon substrate. The trench has a depth of typically in the order of 8 microns and a width of about a quarter micron. A layer of doped, typically arsenic doped, glass (i.e., arsenic doped silicon oxide) is chemically vapor deposited in the trench (i.e., on the sidewalls and bottom of the trench) to a thickness of about 800 A. The doping concentration of the arsenic is typically 2.times.10.sup.21 atoms/cm.sup.3. The structure is then placed in a convection furnace to perform a high temperature anneal. The anneal is carried out at a temperature of about 1050.degree. C. for about 30-60 minutes. The temperature in the furnace increases at a rate of about 4.degree. C. per minute. During the anneal process a portion of the dopant, i.e., arsenic, is diffused from the arsenic layer into the adjacent sidewalls and bottom of the silicon. Thus, an arsenic doped region is formed in the adjacent silicon substrate, providing one of the trench plate capacitor. This plate is referred to as the buried plate. The arsenic concentration in the buried plate is about 5.times.10.sup.19 atoms/cm.sup.3. The furnace is then turned off and the temperature in the furnace cools at a rate of about 5.degree. C. per minute. The arsenic doped glass is removed from the trench using, for example, buffered hydrofluoric acid (HF). Arsenic doped polycrystalline silicon (poly), having a doping concentration of about 1.times.10.sup.20 atoms/cm.sup.3, is then chemically vapor deposited into the trench, i.e., over a dielectric layer formed on the sidewalls and bottom of the silicon substrate. The doped poly serves as the second plate of the capacitor. Thus, a capacitor is formed; the arsenic doped region in the silicon substrate and the doped polycrystalline silicon providing the plates (i.e., electrodes) of the capacitor and the silicon nitride dielectric layer providing the dielectric of the capacitor. The MOSFET is then formed on the substrate adjacent to the trench with the source/drain region of the MOSFET electrically connected to the doped polycrystalline silicon to thereby electrically connect the MOSFET to the capacitor and provide a DRAM cell.
The capacitance of the capacitor is related to the conductivity of its electrodes. Thus, one way to increase the capacitance is to increase the conductivity of one, or both, of the electrodes. As noted above, the arsenic doped glass is doped with a concentration of 2.times.10.sup.21 atoms/cm.sup.3. Further, it is desirable to reduce the size of the capacitor in order to increase the number of cell which may be formed on a chip. However, if the size of the capacitor were reduced by reducing the diameter of the trench, say to a diameter of about 0.15 microns, if the same thickness is used for the arsenic doped glass (i.e., 800 A), since the trench is somewhat tapered, the doped glass will fill the bottom portion of the trench. Thus, the glass layer will be thicker at the bottom portion of the trench than at the sidewalls of the trench. Consequently, when the wet chemical etch is used to remove the glass layer, because the etch rate is the same for both the thicker bottom portion of the glass as the thinner sidewall portion of the glass, the etch time required to remove the bottom portion of the glass will remove portions of the pad silicon oxide layer and produce additional adverse effects to the structure.